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CXA1779P
Predriver for High Resolution Computer Displays For the availability of this product, please contact the sales office.
Description The CXA1779P is a bipolar IC developed for high resolution computer displays. Features * Wide bandwidth (150MHz/-3dB typ.) * RGB single package * Permits RGB common and independent contrast control * Permits RGB independent pedestal level control * Input D-range: 0.7Vp-p (min.) Applications High resolution computer displays Structure Bipolar silicon monolithic IC Block Diagram and Pin Configuration (Top View)
Vcc 1
28 pin DIP (Plastic)
Absolute Maximum Ratings * Supply voltage Vcc 14 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 2.8 W Recommended Operating Conditions Supply voltage Vcc 12 0.6
V
PEDESTAL CLAMP 1.7V BLANK INC ADD OUTPUTBUFFER
28
R OUT
R IN
CLP
2
SYNC SLICE
GAIN +15dB
27 BLK BRIGHTNESS CONTROL 26
R S/H
R DRV
3
R CONTRAST CONTROL PEDESTAL CLAMP 1.7V PIX
R BRT
CLP 25 BLANKING ADD OUTPUTBUFFER 24 BLK BRIGHTNESS CONTROL 23 G S/H G OUT RD GND
R GND
4
G IN
5
CLP
SYNC SLICE
GAIN +15dB
G DRV
6
G CONTRAST CONTROL PIX
CLP 22 G BRT
G GND
7 PEDESTAL CLAMP 1.7V BLANKING ADD SYNC SLICE GAIN +15dB BLK BRIGHTNESS CONTROL OUTPUTBUFFER
B IN
8
21
GO GND
CLP
B DRV
9
20
B OUT
B GND
10
B CONTRAST CONTROL PIX
19 CLP 18 PIX
B S/H
REG
11
B BRT
PIX
12
RGB CONTRAST CONTROL BLK BLANKING PULSESHAPE
17
BO GND
GND
13 CLP
16
BLK
CLP
14
CLAMP PULSESHAPE
15
N.C.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E94510-ST
CXA1779P
Pin Description Pin No. 1 Symbol Vcc Pin voltage 12V Equivalent circuit Description Power supply pin.
2
R IN
Vcc 200A
5
G IN
3.0V
129 2 5 8 129 200A GND
RGB input pins. The pedestal level of the input signal is 3.0V during clamping. Connect 0.01F in series as the clamping capacitor.
8
B IN
3 6 9
R DRV G DRV
Vcc 200A 200A
60k
B DRV
--
3 6 9 12 GND
RGB contrast adjustment pins. The variable range of the pin voltages is from 0 to 5V. RGB simultaneous contrast adjustment pin. The variable range of the pin voltage is from 0 to 5V. GND pins for the input amplifier block.
129
12
PIX
4 7 10
R GND G GND B GND
Vcc
0V
11
REG
5V
11 20k
* Internal regulator stabilizing pin. * 5V regulator output pin. * Attaches the decoupling capacitance (0.01F).
GND
13 17 21 25
GND BO GND GO GND RO GND
0V
GND pin. GND pins for the output stage buffer amplifier block.
0V
-2-
CXA1779P
Pin No.
Symbol
Pin voltage
Equivalent circuit
Vcc
Description
14
CLP
--
14 129 15k
* Clamp pulse input pin. * Turns the input clamp and the bright level adjustment circuit on and off when high. VH = 3V VL = 1.5V
GND
15
N.C.
--
Vcc
Leave this pin open. Connect to GND.
16
BLK
--
16 129 30k
* Blanking pulse input pin. * Threshold level at approximately 2.25V. VH = 3V VL = 1.5V
GND Vcc
18
B BRT
200A
200A
50k
22
G BRT
--
18 22 129 26 GND Vcc
RGB bright level adjustment pins. The variable range of the pin voltages is from 0 to 5V.
26
R BRT
19
B S/H
1k
23
G S/H
19 23 27 100A
Pins to externally attach the sample-and-hold capacitor (0.01F).
27
R S/H
200A GND Vcc
20
B OUT
24
G OUT
20 24 28
RGB output pins.
28
R OUT -3-
GND
CXA1779P
Electrical Characteristics No. 1 Item Current consumption Symbol Icc
(Ta = 25C, Vcc = 12V, See Electrical Characteristics Measurement Circuit.) Measurement contents S1 to S7: OFF Input signal: None S1 to S7: ON Input continuous 1MHz and 100MHz sine waves at 0.7Vp-p, and measure the gain difference of the output amplitudes. Min. 50 Typ. 88 Max. 120 Unit mA
2
Frequency response
f100MHz
Gain difference [dB] = 20log
( VOUT 100M ) VOUT 1M
0.7Vpp
-3
-1.5
--
dB
RGB input signal (RGB input pin)
0.35V CLP potential GND
S1 to S7: OFF Input video signal 0.7Vp-p and measure output signal amplitude VOUT. Calculate the contrast gain from this VOUT. 3 Contrast control CONTMAX [dB] = 20log
CONTMAX
RGB input signal 0.7Vpp
( VOUT ) 0.7
13
14
--
dB
Measuring is possible with or without a sync signal.
S1 to S7: OFF CLP pulse width: 300ns BRTmax Measure the pedestal level of the RGB output signal. 4 Brightness control BRTmin
RGB output signal
--
3.5
--
V
Pedestal level GND Measuring is possible with or without a sync signal.
--
1.9
--
S1 to S7: OFF Input video signal 0.7Vp-p and measure the variable width of output signal VOUT. Gain difference [dB] = 20log DRVgain
RGB output signal
5
Sub contrast gain
VOUT DRVmin ( VOUT DRVmax )
DRVmax DRVmin
--
-6
--
dB
Measuring is possible with or without a sync signal.
-4-
CXA1779P
No.
Item
Symbol
Measurement contents S1 to S7: OFF Measure the level which maintains the output gain when the input video signal level is varied. S1 to S7: OFF Measure the clamp pulse width where the pedestal level of output signal VOUT does not fluctuate.
Min.
Typ.
Max.
Unit
6
Input D-range
D rang
--
0.8
--
Vp-p
7
Minimum clamp pulse width
CLPmin
Video input Pulse width CLP pulse
--
300
--
ns
-5-
CXA1779P
Electrical Characteristics Measurement Circuit
9V
S4 0.01
VOUT
VOUT
VOUT
28
27
26
25
24
23
22
21
20
19
18
17
R GND RO GND
G GND
GO GND
R DRV
G DRV
B DRV
B GND
BO GND
G OUT
R OUT
G BRT
B OUT
R BRT
B BRT
G S/H
R S/H
B S/H
R IN
G IN
REG
GND
Vcc
B IN
PIX
1 10 12V
+
2
3
4
5
6
7
8
9
10
11
12
13
14 S7
4V
0.01
+
0.1
0.01
+
4V
+
0.01
VIN Vcc 10k
S1 1k
VIN Vcc 10k
S2 1k
VIN Vcc 10k
S3 1k
Application Circuit
BLK in
CATHODE DRIVER
5V 0.01 28 27 26 25 24 0.01 23 22
5V 0.01 21 20 19 18
5V
CLP
CLP 16 15
17
N.C.
BLK
R GND RO GND
G GND
GO GND
R DRV
G DRV
B DRV
B GND
BO GND
G OUT
R OUT
G BRT
B OUT
R BRT
B BRT
G S/H
R S/H
B S/H
R IN
G IN
REG
GND
Vcc
B IN
PIX
1 10 12V
2 0.01
3
4
5 0.01
6
7
8 0.01
9
10
11
12
13
14
5V
5V
5V
0.1
5V
R in 0.7Vpp
G in 0.7Vpp
B in 0.7Vpp
CLP in
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
-6-
CLP
N.C.
BLK
+
2.5V
S5
0.01
S6
BLK 0.01
16
15
CXA1779P
Description of Operation 1. Contrast control The contrast for RGB IN (Pins 2, 5 and 8) input signals is adjusted using a DC externally input to the PIX pin (Pin 12). In addition, the contrast for each RGB channel can be adjusted independently using a DC externally input to the DRV pins (Pins 3, 6 and 9). (See Graphs 1 and 2.) 2. Pedestal clamp and brightness control The pedestal clamp clamps the pedestal level when the CLP pin (Pin 14) is high. The RGB IN pin voltage at the pedestal is approximately 3.2V when the pedestal is clamped. The CLP pin threshold level is 3V for VH and 1.5V for VL. (See Fig. 2.) Using a DC externally input to the R, G and B BRT pins (Pins 26, 22 and 18), the brightness control samples and holds the pedestal with the capacitance connected to the RGB SH pins (Pins 27, 23 and 19) when the CLP pin (Pin 14) is high, thereby adjusting the pedestal level of the R, G and B channels. (See Graph 3.) 3. Blanking additional function Output is blanked when the BLK pin (Pin 16) is high. The BLK pin threshold level is 3V for VH and 1.5V for VL. See the Example of Input/Output Signals for output signal levels. The output signal is 0.3V during the blanking interval. (See Figs. 4 and 5.)
-7-
CXA1779P
Example of Input/Output Signals
0.7Vpp (Typ.) RGB IN Pins 2, 5 and 8
Clamp DC voltage 3.2V GND = 0V
Fig. 1
VH = 3V
tCLP
CLP pulse Pin 14
tCLP 300ns VL = 1.5V
Fig. 2
RGB OUT Pins 20, 24 and 28 Adjust the contrast with the PIX and DRV pins. Adjust the pedestal level with the BRT pin. GND When a sync signal is added to the RGB input signal, after the signal is sliced into approximately 60mVp-p inside the IC, it is amplified by the gain from the PIX and DRV pins and output.
Fig. 3
BLK Pin 16
VH = 3V
VL = 1.5V
Fig. 4
RGB OUT Pins 20, 24 and 28 (During BLK pulse input) (When the blanking function is operating) Approximately 0.3V (typ.) GND
Fig. 5 -8-
CXA1779P
Example of Representative Characteristics
Graph 1. Contrast control (RGB common) characteristics
20
Input conditions for each control pin
Output level [dB]
10
Pin name
0
Pin voltage 0 to 5 [V] 4 [V] 4 [V] 4 [V] 2.5 [V] 2.5 [V] 2.5 [V] 0.65 [Vpp]
-10
12 3 6 9 26 22 18 5
0 1 2 3 PIX [V] 4 5
PIX R DRV G DRV B DRV R BRT G BRT B BRT G IN
-20
Graph 2. DRV control (RGB independent) characteristics (Gch)
2
Input conditions for each control pin
0
Output level [dB]
Pin name
-2
Pin voltage 4 [V] 4 [V] 0 to 5 [V] 4 [V] 2.5 [V] 2.5 [V] 2.5 [V] 0.65 [Vpp]
PIX -4
12 3 6 9 26 22 18 5
3 4 5
PIX R DRV G DRV B DRV R BRT G BRT B BRT G IN
-6
0
1
2
G DRV [V]
Graph 3. BRT control characteristics
4
Input conditions for each control pin
Pedestal level [V]
3
Pin name 12 3 6 9 26 22 18 5
1 2 3 4 5
Pin voltage 2.5 [V] 2.5 [V] 2.5 [V] 2.5 [V] 2.5 [V] 0 to 5 [V] 2.5 [V] 0.65 [Vpp]
2
1
PIX R DRV G DRV B DRV R BRT G BRT B BRT G IN
0
G BRT [V]
-9-
CXA1779P
Package Outline
Unit: mm
28PIN DIP (PLASTIC)
+ 0.1 0.05 0.25 -
15
+ 0.4 37.8 - 0.1
28
+ 0.3 13.0 - 0.1
1 2.54
14
0.5 0.1 1.2 0.15
Two kinds of package surface: 1.All mat surface type. 2.Center part is mirror surface.
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER ALLOY 4.2g
SONY CODE EIAJ CODE JEDEC CODE
DIP-28P-03 DIP028-P-0600
- 10 -
3.0 MIN
0.5 MIN
LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
+ 0.4 4.6 - 0.1
15.24
0 to 15

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